Various kinds of semiconductor devices including a single semiconductor chip 51 as shown in FIGS. 38 and 39 have been proposed (prior art 1). This type of semiconductor device is produced in the following manner. That is, the semiconductor chip 51 is mounted onto a die pad 55 formed in a lead frame 54 with a die attachment material 53 of a thermosetting type, such as silver paste (this technique is referred to as die bonding, hereinafter). Then, the die attachment material 53 is set through heat treatment, whereupon the semiconductor 51 is fixed to the die pad 55 (die bonding step).
Then, electrode pads 52 formed on the element forming surface of the semiconductor chip 51 are electrically connected to inner leads 56 formed on the lead frame 54 through bonding wires 59, such as gold wires (wire bonding step). Further, molding resin 60 is applied to mold these components, after which a tie bar (not shown) for preventing the leakage of the molding resin 60 into the spaces among outer leads 57 and support leads 58 for supporting the die pad 55, both formed in the lead frame 54, are disconnected. Finally, the outer leads 57 are bent to form a desired shape (forming), whereby a final product is produced.
A larger memory has been demanded to a semiconductor device while a demand for smaller and lighter electronic equipment has been increasing. Thus, the semiconductor device of the prior art 1 was advanced to a semiconductor device shown in FIGS. 40 and 41, in which two semiconductor chips 51a and 51b are mounted respectively onto both the surfaces (main and back surfaces) of the die pad 55 (prior art 2). This type of semiconductor device is produced in such a manner that the semiconductor chips 51a and 51b oppose each other at their back surfaces (the flip surface of the element forming surface) by a method proposed in, for example, Japanese Patent Application No. 297059/1994 (Tokuganhei No. 6-297059).
To be more specific, the semiconductor chip 51a; is mounted onto one of the surfaces of the die pad 55 with paste of the die attachment material 53, such as silver paste and silver-free paste. Then, the die attachment material 53 is set with heat, whereupon the semiconductor chip 51a is fixed to the die pad 55. Subsequently, the semiconductor chip 51b is mounted onto the other surface of the die pad 55 with the paste of the die attachment material 53, and the die attachment material 53 is set with heat, whereupon the semiconductor chip 51b is fixed to the die pad 55.
Then, electrode pads 52a of the semiconductor chip 51a are bonded to inner leads 56 through the wire bonding with bonding wires 59a, such as gold wires. Likewise, electrode pads 52b of the other semiconductor chip 51b are bonded to the inner leads 56 through the wire bonding with bonding wires 59b. The rest of the steps are carried out in the same manner as the prior art 1.
Incidentally, in case of the conventional semiconductor device of the prior art 2, in which the semiconductor chips 51a and 51b are mounted respectively onto both the surfaces of the die pad 55 and thereby increasing a memory capacity two times, the length and angle of the bonding wires 59a and 59b depend on the layout of the electrode pads 52a and 52b. In other words, the bonding wires 59a and 59b may be extended considerably or the adjacent wires may cross each other depending on the positions of the electrode pads 52a and 52b. When this happens, the bonding wire 59a may cause a short-circuit with the semiconductor chip 51a or adjacent wire, or a phenomenon known as opening (the disconnection or the like) due to the stress applied during the molding using the molding resin.
Thus, in case that the semiconductor chips 51a and 51b are of the same kind (chips having the same chip size, using the same kind of silicon substrates, and operating at the same substrate potential), as shown in FIG. 40, element circuit patterns (including the electrode pads 52a and 52b) respectively formed on the semiconductor chips 51 and 51b must be mirror-reversed to each other.
On the other hand, in case that the semiconductor chips 51a and 51b are of different kinds (chips having different chip sizes, using different kinds of silicon substrates, and operating at different substrate potentials), the arrangement of either or both the electrode pads 52a and 52b on the semiconductor chips 51a and 51b must be modified, because the original electrode pads 52a and 52b are formed indiscriminately.
Thus, according to the conventional 2-chip-1-package semiconductor device, the design of at least one of the semiconductor chips 51a and 51b must be modified to eliminate the problem caused by the layout of the electrode pads 52a and 52b. Consequently, there arises a problem that it takes longer to develop the device.
The above inconvenience can be eliminated by simply changing the position of either of the electrode pads 52a or 52b regardless of whether the semiconductor chips 51a and 51b are of the same or different kinds. However, this method involves too much wiring, thereby arising another problem that the semiconductor chips 51a and 51b are further upsized compared with the method of modifying the entire design.
Japanese Laid-open Patent Application No. 151641/1994 (Tokukaihei No. 6-151641) discloses a semiconductor device which can avoid the aforementioned problem caused by the layout of the electrode pads 52a and 52b. In this semiconductor device, as shown in FIG. 42, an insulation circuit substrate 64 is bonded to an island 63 of lead frames 62 through the die bonding with paste or the like in such a manner to encircle an array semiconductor chip 61. A first pad 65 serving as an electrode pad in the array semiconductor chip 61 is electrically connected to one of the lead frames 62 through a first terminal 67 forming a part of a connecting band 66 on the insulation circuit substrate 64.
According to the above arrangement, flexibility is allowed to the line linking method of the first pad 65 and lead frame 62, thereby making it easier to design the lead frames 62 for a multi-chip or the like onto which a plurality of chips are mounted.
However, in the above semiconductor device, the semiconductor chip is mounted onto the one surface of the die pad alone, and if a memory capacity is increased by mounting a plurality of the semiconductor chips on the one surface of the die pad, the IC packaging area is increased as well. Also, since the wires are provided to encircle the array semiconductor chip 61 in the above semiconductor device, the number of the wires is limited. Thus, the above semiconductor device may not be produced with some particular kinds of chips. Further, with the above semiconductor device, only the array semiconductor chip 61 is concerned, and for example, the stacked structure or the like using a combination of any kind of semiconductor chips, is not concerned. Hence, there arises a problem that a more versatile semiconductor device can not be provided.